Dual gate integrated circuits having both high voltage (HV) devices, which may also be referred to herein as input/output (I/O) devices, and low voltage (LV), or core, devices have gained wide acceptance and utility in the semiconductor industry since their introduction. In addition, however, there is a great demand for shrinking these semiconductor devices to provide an increased device density on the semiconductor chip and provide chips that are faster and consume less power. In fact, to provide the required device performance, the scaling of the gate dielectric thickness in these devices has now reached below 2.5 nm.
However, simply scaling standard dielectrics while maintaining good process control in this thickness regime is very difficult. Thus, the industry is left with the desire to use thicker films that are correspondingly easier to control to tight limits, while using the existing equipment, and decreasing the electrical dielectric thickness to increase device performance (increase IDS) with less leakage and without degradation to long channel threshold voltages.
To achieve these goals, the industry has turned to the use of high dielectric constant (high-k) materials. One such high-k film that has found popular utility is a plasma nitridated oxide or PNO. In this process, a remote or decoupled nitrogen plasma or other known method for nitridation is used to implant a dielectric with uniformly high doses of nitrogen. The addition of this nitrogen effectively increases the dielectric constant value of the gate dielectric, thus allowing a physically thicker film to be electrically thinner.
Initially, these plasma nitridation processes were used for the LV device due to the fact that its gate dielectric thickness was thinner than the gate dielectric of the HV device. Thus, a high-k material for the HV devices was not required because the overall scale of the integrated circuit had not reached the point that required the use of such a material in the I/O area. As such, plasma nitridation was not used on the high voltage area, but with the advent of less than 2.5 nm HV devices, nitridation of the HV region is now highly desirable for a fully robust device.
Unfortunately, however, the industry has been experiencing problems when both the HV gate dielectric and LV gate dielectric are nitridated. More specifically, the industry has begun to notice a roughing of the underlying base silicon in the LV device area. FIG. 1 is a transmission electron microscope (TEM) photo of a silicon surface 10 wherein the LV layer 15 was formed using a dual plasma nitridation process in which both the HV gate dielectric and the LV gate dielectric were nitridated. As seen in this figure, the silicon surface 10 is irregular or roughened at 10a. Layer 17 is a poly gate electrode subsequently formed on top of the previously roughened LV dielectric. This condition is highly undesirable because roughened silicon has several disadvantages, including lower intrinsic reliability, additional variation in the optical thickness measurements used for inline process control, and increase variation in ramped voltage breakdown metrics.
Accordingly, what is needed in the art is a method of manufacturing an integrated circuit that does not produce a roughened silicon surface when subjected to a dual plasma nitridation process.